Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind

Authors

  • Arif Ul Alam Department of Electronics and Telecommunication Engineering, University of Liberal Arts Bangladesh
  • Nishatul Majid Department of Electronics and Telecommunication Engineering, University of Liberal Arts Bangladesh
  • SK Aditya Department of Applied Physics, Electronics & Communication Engineering, University of Dhaka, Dhaka

DOI:

https://doi.org/10.3329/dujs.v60i1.10346

Abstract

A good deal of ingenuity can be exercised and a vast amount of time wasted exploring layout topologies to minimize the size of a gate or other circuitry such as an adder or memory element in an integrated circuit. This paper represents a simple and compact layout design for two bit binary parallel ripple carry adder using only CMOS NAND gates with the help of Microwind as a tool for design and simulation. Construction of this adder for fabricating involves the design of 2-input, 3-input, 4-input NAND gates and CMOS NAND inverters. The performance parameters are analyzed from the simulation responses and characteristics curves of the proposed design. The optimization of the design towards single P+ or N+ diffusion, single +Vdd and single Vdd supply contributed to lesser area and improved functionality of the adder circuits performance.

DOI: http://dx.doi.org/10.3329/dujs.v60i1.10346  

Dhaka Univ. J. Sci. 60(1): 103-108 2012 (January)  

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Published

2012-04-15

How to Cite

Ul Alam, A., Majid, N., & Aditya, S. (2012). Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind. Dhaka University Journal of Science, 60(1), 103–108. https://doi.org/10.3329/dujs.v60i1.10346

Issue

Vol. 60 No. 1 (2012)

Section

Articles