Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design
DOI:
https://doi.org/10.3329/gubjse.v7i0.54025Keywords:
K-map, Digital Logic Design, Quine McCluskey(QM) technique, C minimizerAbstract
In computerized integrated circuits, the fundamental principle intends to avoid the multifaceted nature of the circuitry by making it as brief as attainable and minimize the expenditure. Techniques like Quine- McCluskey (QM) and Karnaugh Map (K-Map) are often used approaches of simplifying Boolean functions. This study presents a recreation framework of simplification of the Boolean capacities by the utilize of the K- Map definition for beginner-level learners. It uses the algebraic expression of the Boolean function to decrease the number of terms, generates a circuit, and does not use any redundant sets. In this way, it gets to be competent to deal with lots of parameters and minimize the computational cost. The result of the assessment is performed in this paper by contrasting it with the C- Minimizer algorithm. In computation time terms, the result appears that our comprehensive K mapping tool outflanks in current procedures, and the relative error accomplishes a lower rate of percentage (2%), which fulfills the satisfactory level.
GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 7, Dec 2020 P 76-84
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