Hardware implementation issues of turbo decoders

Authors

  • MS Islam Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka
  • MA Quaium Department of Electrical Engineering, Technical University of Delft
  • M Morshed Department of Electrical and Electronic Engineering, Ahsanullah University of Science and Technology, Dhaka
  • RC Roy Pilot Plant and Process Development Center (PP & PDC), BCSIR, Dhaka

DOI:

https://doi.org/10.3329/bjsir.v47i3.13068

Keywords:

SCCC, SOVA, PCCC, SISO, LLR

Abstract

This paper gives a general overview of the implementation aspects of turbo decoders. Although the parallel architecture of the turbo code is emphasized, the serial concatenated convolutional codes for the turbo decoder are discussed too. Considering the general structure of iterative decoders, the main features of the soft input and soft output algorithm, which are the heart of a turbo decoder, are observed. The efficient parallel architectures of turbo decoders are shown which allow high speed implementation. Apart from these, implementation aspects like quantization issues and stopping rules to increase the throughput as well as an evaluation of the various turbo decoders are discussed. Finally, we suggest a number of solutions to overcome the implementation issues as well as the complexities without affecting the high throughput rate.

DOI: http://dx.doi.org/10.3329/bjsir.v47i3.13068

Bangladesh J. Sci. Ind. Res. 47(3), 327-332 2012

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Published

2012-12-21

How to Cite

Islam, M., Quaium, M., Morshed, M., & Roy, R. (2012). Hardware implementation issues of turbo decoders. Bangladesh Journal of Scientific and Industrial Research, 47(3), 327–332. https://doi.org/10.3329/bjsir.v47i3.13068

Issue

Vol. 47 No. 3 (2012)

Section

Articles

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